The present invention relates to a semiconductor integrated circuit technique and, more particularly, to a technique which may effectively be applied to logic LSI's (large-scale integration circuits), for example, a logic LSI having a RAM (random-access memory) as a main constituent element and logic circuits as peripheral elements.
When a system such as a computer is arranged by a combination of a general-purpose RAM and gate arrays, it is conventional practice to allow LSI's to exchange signals of ECL level having a relatively large amplitude or signal voltage, which is known as "ten K" (hereinafter referred to as "10k") or "hundred K" (hereinafter referred to as "100k").
In the case where a system such as a control storage of a computer is arranged using, for example, a RAM, a logic section L1 such as an address latch circuit may be connected to the input side of the RAM, and a logic section L2 such as an error correct circuit known as "ECC" or a signal select circuit may be connected to the output side of the RAM, as shown in FIG. 5. It should be noted that the RAM consists of an input buffer IB, an address decoder DEC, a MEMORY cell array MCARY, a sense gate SG, an output buffer OB, etc.
When such memory system is arranged, since conventional general-purpose RAM's have no peripheral logic circuits, the peripheral logic sections L1 and L2 must be arranged using logic LSI's such as gate arrays.
Accordingly, signals which are exchanged between the logic section L1 and the RAM and between the logic section L2 and the RAM are set at an ECL level of 10k or 100k which is specified as a signal level between LSI's.
In such case, since the amplitude or signal voltage of the ECL level, i.e., 10k or 100k, is greater than that of signals employed inside the RAM and the gate arrays, it is necessary to respectively provide an output buffer OB involving a relatively large drive power and an input buffer IB having a level shift function at output and input ports of the RAM and the logic sections. Accordingly, the above-described memory system involves a considerably long delay in the input and output buffers.
On the other hand, it is desired to achieve an increased speed of the memory system of the type described above. However, the speed of signals employed inside the RAM and the gate arrays has already been increased to a considerable extent and almost reached the technical limit.